IITB-RISC — a 6-stage pipelined processor
A 16-bit pipelined CPU in VHDL: eight registers, three instruction formats, six stages, and the forwarding and interlock logic needed to keep them fed.
IITB-RISC is a 16-bit machine in the Little Computer tradition: eight general purpose registers, byte addresses, two bytes fetched per instruction, and three formats — register, immediate and jump — sharing a four-bit opcode.
The design work is not the instruction set. It is the six stages — fetch, decode, register read, execute, memory, write back — and everything that goes wrong once instructions overlap. An instruction reading a register that a previous instruction has not written yet is a hazard, and the datapath is mostly the machinery for detecting and resolving those.
The condition codes needed a decision of their own. The carry and zero flags are registered, but the controller has to see the flags a previous instruction set before the clock edge that commits them — so the datapath exposes them as CP and ZP, “carry past” and “zero past”, alongside the combinational CC and ZC that will become the next state.
There is no branch predictor. Every branch is taken as a stall. It would slot into the existing datapath and it is the obvious next thing, along with a few smaller optimisations — I stopped at a correct pipeline rather than a fast one.
The repository has the VHDL, the full datapath drawing as SVG, the instruction encoding, and the report.
Gallery
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